1. Field of the Invention
This invention relates to a data storing device used as an I/O (input/output) register of a single-chip microcomputer, for example, and more particularly to a data storing device having a plurality of registers allotted for one address.
2. Description of the Related Art
In general, in the I/O register of a single-chip microcomputer, one address is assigned to each register and only one register corresponding to a designated address can be accessed. In FIG. 1, the construction of an extracted portion of the above I/O register section and the peripheral circuit thereof is shown. A 16-bit address signal AD is input to an address decoder section 12 via an address bus 11. The address signal AD is decoded by the address decoder section 12 which in turn outputs a decoder signal ADOn (n=1, 2, 3, . . . ). 8-bit data stored in a register Rn (n=1, 2, 3, . . . ) corresponding to an address An (n=1, 2, 3, . . . ) designated by the signal ADOn is output in synchronism with the rise (or fall) of an R/W (read/write) control signal S and then transferred along a data bus 13.
However, with the above construction, when an attempt is made to increase the number of I/O registers to expand the register area, it is required to make various modifications for the address area. For example, when address areas allotted for the RAM and ROM are provided to follow an address area allotted for the I/O register, the address areas for the RAM and ROM must be modified in order to expand the register area. Otherwise, it becomes necessary to provide an additional register area in an address area arranged after the address area for the RAM or ROM.
In the former case, a large-scale modification is necessary and the specification must be greatly modified. Further, in the latter case, the modification scale can be made small, but the I/O register area is not continuous and becomes hard to deal with.